A method for forming a metal wire interconnection in a semiconductor device is disclosed, and more particularly, a method for preventing a diffused reflection from being generated in patterning a via hole for the metal interconnection is disclosed.
Generally, the xe2x80x9cDamascenexe2x80x9d process is to form a semiconductor wire by using the etch-back process or the chemical mechanical polishing (CMP) process in a semiconductor fabricating method. In the Damascene process, an insulation layer is etched in the form of a wire by the photolithography process and then a recess is formed with a predetermined depth. The recess is filled with a conducting layer, such as a tungsten layer, and the undesired conducting layer is etched back by using the etch-back process or the chemical mechanical polishing (CMP) process.
This technique has been used for forming bit lines and word lines in a DRAM devices. In the case where the Damascene process is used for the bit lines in DRAM devices, the recesses are formed in an insulation layer along the metal wires of the bit lines and contact holes for connecting the metal wires to a semiconductor substrate are also formed by the photolithography process. Subsequently, the recesses and the contact holes are filled with metal materials and the undesired metal materials on the insulation layer are removed.
In the case where the bit lines are formed by the Damascene process, the interconnection between the bit line and an active region of the semiconductor substrate is simultaneously formed with the metal wire and then topology caused by other adjacent layers may be improved with facility of the following processing steps.
On the other hand, in the semiconductor fabricating method, the metal layers are formed in a dual structure or in a multi-structure and typically, the metal layers are made of aluminum. Accordingly, the aluminum layer has a high reflexibility which causes the reflected light for patterning the aluminum layer to make the notching or thinning thereof. With the increase of the integration in semiconductor devices, this problem more appears because of the narrow width of the metal layer.
FIGS. 1A to 1D are cross-sectional views illustrating a method for forming a via first which is widely used in a conventional Damascene process. Referring to FIG. 1A, a first SiN layer 12, as an etching stopper, is formed on a semiconductor substrate 11 on which predetermined processes have been carried out. A first SiO2 layer 13 is formed on the first SiN layer 12, a second SiN layer 14, as an etching stop layer, is formed on the SiO2 layer 13 in a contact level of the topology, and then a second SiO2 layer 15 is formed on the second SiN layer 14. Photoresist patterns 16 are formed on the second SiO2 layer 15 using a photoresist layer.
Referring to FIG. 1B, the second SiO2 layer 15, the second SiN layer 14 and the first SiO2 layer 13 are selectively etched using the photoresist patterns 16 as an etching mask layer, thereby forming a via hole 17.
Referring to FIG. 1C, an organic anti-reflecting coating layer (ARC) 18 is formed on the resulting structure in order to prevent the pattern profile from being deteriorate by a diffused reflection in the via hole 17. The ARC layer 18 is also deposited on the bottom of the via hole 17 and has a viscosity such that a layer of approximately 900 xc3x85 will be deposited at a spin rate of 3000 rpm with a resulting thickness of approximately 1000 xc3x85 to 1400 xc3x85. In the case where the size of the via hole 17 is not sufficient for a deposition process, the via hole 17 is not completely filled with the ARC layer 18. Typically, the ARC layer 18 is deposited in a track, which is one of steppers, using a spinner. Subsequently, a photoresist layer is formed on the ARC layer 18 and patterned so as to form photoresist patterns 19 exposing a portion of the ARC layer 18 around the via hole 17.
Referring to FIG. 1D, the exposed ARC layer 18 and the second SiO2 layer 15 are etched using the photoresist patterns 19 as an etching mask, thereby forming a final step-type via hole 20. In the etching process, the ARC layer 18 may prevent the loss of the via hole 17 as well as the diffused reflection. A conducting layer (not shown) is deposited on the resulting structure including the via hole 20 and patterned by the etch-back process or the chemical mechanical polishing process so that the conducting layer, such as a metal wire, a word line or a bit line, remains only within the via hole 20.
As stated above, the Damascene process forms the conducting layer after forming the via hole in the insulation layer. Therefore, the metal interconnection and the via hole for electrically connecting one metal layer to the other metal layer are simultaneously formed. However, in the case where the high-viscosity ARC layer is used in a small-sized vial hole based on the development of the exposure techniques and in a miniaturized chip, it is impossible to obtain a sufficient step-coverage of the ARC layer for preventing the diffused reflection within the via hole.
A method for forming metal wires of semiconductor devices using a dual Damascene process to obtain a sufficient filling of an organic anti-reflecting coating layer (ARC) is disclosed.
A method for forming highly integrated circuits by preventing a diffused reflection generated over an under layer of a photoresist layer is also disclosed.
A method for forming a metal wire using a Damascene process is disclosed which comprises forming an insulation layer on a semiconductor substrate, wherein elements for operating a semiconductor device are formed on the semiconductor substrate; forming first photoresist patterns on the insulation layer; etching the insulation layer in order to form a first via hole using the first photoresist patterns and then forming a resulting structure; coating a first anti-reflecting coating layer on the resulting structure with a low viscosity; coating a second anti-reflecting coating layer on the resulting structure with a low viscosity; forming second photoresist patterns on the second anti-reflecting coating layer; and forming a second via hole using the second photoresist patterns.